1. Field of the Invention
The present disclosure relates to a semiconductor device having a large metal wiring and an insulating layer made of organic material.
2. Description of the Relates Art
A dual inline package or a quad flat package, in which a semiconductor chip is sealed with resin, is used as conventional semiconductor package structures. In these semiconductor package structures, a metal lead wiring is mainly provided on a side of the resin package. Meanwhile, recently, a chip scale package (CSP) has quickly become widespread as a semiconductor package structure. This package employs a ball grid array (BGA) technique in which electrodes are planarly disposed on a flat surface of the package, so that an area of the package is almost the same as an area of the semiconductor chip. According to the chip scale package, a semiconductor chip can be densely mounted on an electronic circuit substrate in smaller area than conventional one while the semiconductor chip has the same number of electrode terminals and the same projected area as the conventional one.
The chip scale package is a packaging method including cutting a silicon wafer, on which circuits have been formed, into semiconductor chips, and then packaging the respective semiconductor chips individually.
Meanwhile, according to a method for manufacturing a wafer level CSP, an insulating layer, a rewiring layer, and a sealing layer are sequentially formed on a silicon wafer, and a solder bump is formed. Furthermore, in a final process, the wafer is cut into semiconductor chips each having a predetermined size, whereby the packaged chips are provided.
According to a conventional semiconductor device, a photo-sensitive organic film used as an insulating layer is made of polyimide or benzocyclobutene (BCB). In addition, a rewiring layer is made of copper (Cu) in many cases.
FIG. 17 is a cross-sectional view of an main part of the conventional semiconductor device. As shown in FIG. 17, according to the conventional semiconductor device, plurality of metal wirings 4 are formed on semiconductor substrate 1, and insulating film 2 is provided so as to cover metal wirings 4. Upper metal wiring 5 is provided on insulating film 2, and sealing resin 3 and solder bump 6 are formed on metal wiring 5.
According to the conventional semiconductor device, a difference in thermal stress is generated between insulating film 2, metal wirings 4 and 5, and semiconductor substrate 1, due to heat of a heat treatment, for example connecting solder bump 6, in a manufacturing process. A physical factor due to the thermal stress difference and mechanical outer force cause a connection defect between solder bump 6 and semiconductor substrate 1. This connection defect makes reliability of the semiconductor device decrease.
Thus, as shown in FIG. 18, in order to prevent metal wiring 11 from being peeled from insulating film 8 provided under metal wiring 11, wedge 13 is proposed to be provided in a lower portion of metal wiring 11 (refer to, for example, Unexamined Japanese Patent Publication No. 2004-207324). Thus, when wedge 13 provided in metal wiring 11 is inserted in insulating film 8, insulating film 8 and metal wiring 11 can be strongly adhered to each other, so that solder bump 12 and metal wiring 11 can be prevented from being peeled from each other due to the stress, which enhances the reliability of the semiconductor device.
As described above, solder bump 12 can improve its bump-shear strength and bump-pull strength, so that reliability with respect to the stress caused by a difference in thermal expansion coefficient can be improved in the semiconductor device.